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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Chisel (programming language)</span></span>
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</style><table class="infobox vevent"><tbody><tr><th colspan="2" class="infobox-above" style="background-color:#e0e0e0;">Constructing Hardware in a Scala Embedded Language (Chisel)</th></tr><tr><td colspan="2" class="infobox-image"><span typeof="mw:File"></span></td></tr><tr><th scope="row" class="infobox-label"><a href="Programming_paradigm" title="Programming paradigm">Paradigms</a></th><td class="infobox-data"><a href="Multi-paradigm_programming_language" class="mw-redirect" title="Multi-paradigm programming language">Multi-paradigm</a>: <a href="Concurrent_programming" class="mw-redirect" title="Concurrent programming">concurrent</a>, <a href="Functional_programming" title="Functional programming">functional</a>, <a href="Imperative_programming" title="Imperative programming">imperative</a>, <a href="Object-oriented_programming" title="Object-oriented programming">object-oriented</a></td></tr><tr><th scope="row" class="infobox-label">Family</th><td class="infobox-data"><a href="Scala_(programming_language)" title="Scala (programming language)">Scala</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Software_developer" class="mw-redirect" title="Software developer">Developer</a></th><td class="infobox-data organiser"><a href="University_of_California%2C_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a></td></tr><tr><th scope="row" class="infobox-label">First&nbsp;appeared</th><td class="infobox-data">June&nbsp;2012<span style="display:none">&nbsp;(<span class="bday dtstart published updated">2012-06</span>)</span></td></tr><tr><td colspan="2" class="infobox-full-data"></td></tr><tr><th scope="row" class="infobox-label" style="white-space: nowrap;"><a href="Software_release_life_cycle" title="Software release life cycle">Stable release</a></th><td class="infobox-data"><div style="margin:0px;">3.6.0
/ April&nbsp;14, 2023<span style="display:none">&nbsp;(<span class="bday dtstart published updated">2023-04-14</span>)</span></div></td></tr><tr style="display:none"><td colspan="2">
</td></tr><tr><th scope="row" class="infobox-label"><a href="Type_system" title="Type system">Typing discipline</a></th><td class="infobox-data"><a href="Type_inference" title="Type inference">Inferred</a>, <a href="Static_typing" class="mw-redirect" title="Static typing">static</a>, <a href="Strong_and_weak_typing" title="Strong and weak typing">strong</a>, <a href="Structural_type_system" title="Structural type system">structural</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Scope_(computer_science)" title="Scope (computer science)">Scope</a></th><td class="infobox-data"><a href="Scope_(computer_science)" title="Scope (computer science)">Lexical</a> (static)</td></tr><tr><th scope="row" class="infobox-label">Implementation language</th><td class="infobox-data"><a href="Scala_(programming_language)" title="Scala (programming language)">Scala</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Computing_platform" title="Computing platform">Platform</a></th><td class="infobox-data"><a href="Java_virtual_machine" title="Java virtual machine">Java virtual machine</a> (JVM)<br><a href="JavaScript" title="JavaScript">JavaScript</a> (<a rel="nofollow" class="external text" href="https://scala-js.org">Scala.js</a>)<br><a href="LLVM" title="LLVM">LLVM</a> (<a rel="nofollow" class="external text" href="https://scala-native.org/">Scala Native</a>) (experimental)</td></tr><tr><th scope="row" class="infobox-label"><a href="Software_license" title="Software license">License</a></th><td class="infobox-data"><a href="Apache_License" title="Apache License">Apache License</a> 2.0</td></tr><tr><th scope="row" class="infobox-label">Website</th><td class="infobox-data"><span class="url"><a rel="nofollow" class="external text" href="http://www.chisel-lang.org">www<wbr>.chisel-lang<wbr>.org</a></span></td></tr></tbody></table>
<p><b>Chisel</b> (an <a href="Acronym" title="Acronym">acronym</a> for <b>Constructing Hardware in a Scala Embedded Language</b><sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>) is an <a href="Open-source" class="mw-redirect" title="Open-source">open-source</a> <a href="Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL) used to describe <a href="Digital_electronics" title="Digital electronics">digital electronics</a> and circuits at the <a href="Register-transfer_level" title="Register-transfer level">register-transfer level</a>.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>
</p><p>Chisel is based on <a href="Scala_(programming_language)" title="Scala (programming language)">Scala</a> as a <a href="Domain-specific_language" title="Domain-specific language">domain-specific language</a> (DSL). Chisel inherits the <a href="Object-oriented_programming" title="Object-oriented programming">object-oriented</a> and <a href="Functional_programming" title="Functional programming">functional programming</a> aspects of Scala for describing digital hardware. Using Scala as a basis allows describing circuit generators. High quality, free access documentation exists in several languages.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
</p><p>Circuits described in Chisel can be converted to a description in <a href="Verilog" title="Verilog">Verilog</a> for <a href="Logic_synthesis" title="Logic synthesis">synthesis</a> and <a href="Logic_simulation" title="Logic simulation">simulation</a>.
</p>
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<div class="mw-heading mw-heading2"><h2 id="Code_examples">Code examples</h2></div>
<p>A simple example describing an <a href="Adder_(electronics)" title="Adder (electronics)">adder</a> circuit and showing the organization of components in Module with <a href="Input/output" title="Input/output">input and output</a> ports:
</p>
<div class="mw-highlight mw-highlight-lang-scala mw-content-ltr" dir="ltr"><pre><span class="k">class</span><span class="w"> </span><span class="nc">Add</span><span class="w"> </span><span class="k">extends</span><span class="w"> </span><span class="nc">Module</span><span class="w"> </span><span class="p">{</span>
<span class="w"> </span><span class="kd">val</span><span class="w"> </span><span class="n">io</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nc">IO</span><span class="p">(</span><span class="k">new</span><span class="w"> </span><span class="nc">Bundle</span><span class="w"> </span><span class="p">{</span>
<span class="w"> </span><span class="kd">val</span><span class="w"> </span><span class="n">a</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nc">Input</span><span class="p">(</span><span class="nc">UInt</span><span class="p">(</span><span class="mi">8</span><span class="p">.</span><span class="nc">W</span><span class="p">))</span>
<span class="w"> </span><span class="kd">val</span><span class="w"> </span><span class="n">b</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nc">Input</span><span class="p">(</span><span class="nc">UInt</span><span class="p">(</span><span class="mi">8</span><span class="p">.</span><span class="nc">W</span><span class="p">))</span>
<span class="w"> </span><span class="kd">val</span><span class="w"> </span><span class="n">y</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nc">Output</span><span class="p">(</span><span class="nc">UInt</span><span class="p">(</span><span class="mi">8</span><span class="p">.</span><span class="nc">W</span><span class="p">))</span>
<span class="w"> </span><span class="p">})</span>

<span class="w"> </span><span class="n">io</span><span class="p">.</span><span class="n">y</span><span class="w"> </span><span class="o">:=</span><span class="w"> </span><span class="n">io</span><span class="p">.</span><span class="n">a</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="n">io</span><span class="p">.</span><span class="n">b</span>
<span class="p">}</span>
</pre></div>
<p>A 32-bit register with a reset value of 0:
</p>
<div class="mw-highlight mw-highlight-lang-scala mw-content-ltr" dir="ltr"><pre><span class="kd">val</span><span class="w"> </span><span class="n">reg</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nc">RegInit</span><span class="p">(</span><span class="mi">0</span><span class="p">.</span><span class="nc">U</span><span class="p">(</span><span class="mi">32</span><span class="p">.</span><span class="nc">W</span><span class="p">))</span>
</pre></div>
<p>A <a href="Multiplexer" title="Multiplexer">multiplexer</a> is part of the Chisel library:
</p>
<div class="mw-highlight mw-highlight-lang-scala mw-content-ltr" dir="ltr"><pre><span class="kd">val</span><span class="w"> </span><span class="n">result</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="nc">Mux</span><span class="p">(</span><span class="n">sel</span><span class="p">,</span><span class="w"> </span><span class="n">a</span><span class="p">,</span><span class="w"> </span><span class="n">b</span><span class="p">)</span>
</pre></div>
<div class="mw-heading mw-heading2"><h2 id="Use">Use</h2></div>
<p>Although Chisel is not yet a mainstream hardware description language, it has been explored by several companies and institutions. The most prominent use of Chisel is an implementation of the <a href="RISC-V" title="RISC-V">RISC-V</a> instruction set, the open-source Rocket chip.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>
Chisel is mentioned by the Defense Advanced Research Projects Agency (<a href="DARPA" title="DARPA">DARPA</a>) as a technology to improve the efficiency of electronic design, where smaller design teams do larger designs.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> <a href="Google" title="Google">Google</a> has used Chisel to develop a <a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> for <a href="Edge_computing" title="Edge computing">edge computing</a>.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Some developers prefer Chisel as it requires one-fifth as much code and is much faster to develop than Verilog.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>
</p><p>Circuits described in Chisel can be converted to a description in <a href="Verilog" title="Verilog">Verilog</a> for <a href="Logic_synthesis" title="Logic synthesis">synthesis</a> and <a href="Logic_simulation" title="Logic simulation">simulation</a> using a program named FIRRTL.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div>
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<ul><li><a href="VHDL" title="VHDL">VHDL</a></li>
<li><a href="Verilog" title="Verilog">Verilog</a></li>
<li><a href="SystemC" title="SystemC">SystemC</a></li>
<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a></li></ul>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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</style><cite id="CITEREFBachrachVoRichardsLee2012" class="citation conference cs1">Bachrach, J.; Vo, H.; Richards, B.; Lee, Y.; Waterman, A.; Avižienis, R.; Wawrzynek, J.; Asanović, K. (June 2012). <span class="id-lock-subscription" title="Paid subscription required"><a rel="nofollow" class="external text" href="https://dl.acm.org/doi/abs/10.1145/2228360.2228584">"Chisel: constructing hardware in a Scala embedded language"</a></span>. <i>Proceedings of the 49th Annual Design Automation Conference (DAC 2012)</i>. San Francisco, California, US: <a href="Association_for_Computing_Machinery" title="Association for Computing Machinery">Association for Computing Machinery</a> (ACM). pp.&nbsp;<span class="nowrap">1216–</span>25. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2228360.2228584">10.1145/2228360.2228584</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a>&nbsp;<bdi>978-1-4503-1199-1</bdi>.</cite></span>
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</li>
<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text">
<cite id="CITEREFMoore2018" class="citation news cs1">Moore, Samuel K. (2018-07-16). <a rel="nofollow" class="external text" href="https://spectrum.ieee.org/darpas-planning-a-major-remake-of-us-electronics-pay-attention">"DARPA Plans a Major Remake of U.S. Electronics"</a>. <i>IEEE Spectrum</i>. <a href="Institute_of_Electrical_and_Electronics_Engineers" title="Institute of Electrical and Electronics Engineers">Institute of Electrical and Electronics Engineers</a> (IEEE)<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-06-10</span></span>.</cite></span>
</li>
<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text">
<cite class="citation audio-visual cs1">Derek Lockhart, Stephen Twigg, Ravi Narayanaswami, Jeremy Coriell, Uday Dasari, Richard Ho, Doug Hogberg, George Huang, Anand Kane, Chintan Kaur, Tao Liu, Adriana Maggiore, Kevin Townsend, Emre Tuncer (2018-11-16). <a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=x85342Cny8c"><i>Experiences Building Edge TPU with Chisel</i></a><span class="reference-accessdate">. Retrieved <span class="nowrap">2020-06-10</span></span>.</cite></span>
</li>
<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cnx-software.com/2021/07/05/xiangshan-open-source-64-bit-risc-v-processor-rival-arm-cortex-a76/">"XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 - CNX Software"</a>. <i>CNX Software - Embedded Systems News</i>. 2021-07-05<span class="reference-accessdate">. Retrieved <span class="nowrap">2022-03-26</span></span>.</cite></span>
</li>
<li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.chisel-lang.org/">"Chisel/FIRRTL Hardware Compiler Framework"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2022-09-08</span></span>.</cite></span>
</li>
</ol></div></div>
<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>
<ul><li><span class="official-website"><span class="url"><a rel="nofollow" class="external text" href="http://www.chisel-lang.org">Official website</a></span></span></li>
<li><a rel="nofollow" class="external text" href="https://github.com/chipsalliance/chisel3">Chisel 3</a> on <a href="GitHub" title="GitHub">GitHub</a></li>
<li><a rel="nofollow" class="external text" href="https://www.youtube.com/channel/@Chisel-lang"><span class="">Chisel</span>'s channel</a> on <a href="YouTube_channel_(identifier)" class="mw-redirect" title="YouTube channel (identifier)">YouTube</a></li></ul>
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</style><div id="Programmable_logic116" style="font-size:114%;margin:0 4em"><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li>
<li><a href="System_on_a_chip" title="System on a chip">SoC</a></li>
<li><a href="Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>
<ul><li><a href="Logic_block" title="Logic block">Logic block</a></li></ul></li>
<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li>
<li><a href="Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li>
<li><a href="Programmable_logic_array" title="Programmable logic array">PLA</a></li>
<li><a href="Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li>
<li><a href="Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li>
<li><a href="Cypress_PSoC" title="Cypress PSoC">PSoC</a></li>
<li><a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>
<ul><li><a href="Xputer" title="Xputer">Xputer</a></li></ul></li>
<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>
<li><a href="Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>
<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>
<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Verilog" title="Verilog">Verilog</a>
<ul><li><a href="Verilog-A" title="Verilog-A">A</a></li>
<li><a href="Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li>
<li><a href="VHDL" title="VHDL">VHDL</a>
<ul><li><a href="VHDL-AMS" title="VHDL-AMS">AMS</a></li>
<li><a href="VHDL-VITAL" class="mw-redirect" title="VHDL-VITAL">VITAL</a></li></ul></li>
<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a>
<ul><li><a href="SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li>
<li><a href="SystemC" title="SystemC">SystemC</a></li>
<li><a href="Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li>
<li><a href="Handel-C" title="Handel-C">Handel-C</a></li>
<li><a href="Lola_(computing)" title="Lola (computing)">Lola</a></li>
<li><a href="Property_Specification_Language" title="Property Specification Language">PSL</a></li>
<li><a href="Unified_Power_Format" title="Unified Power Format">UPF</a></li>
<li><a href="PALASM" title="PALASM">PALASM</a></li>
<li><a href="Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li>
<li><a href="Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li>
<li><a href="C_to_HDL" title="C to HDL">C to HDL</a></li>
<li><a href="Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li>
<li><a href="MyHDL" title="MyHDL">MyHDL</a></li>
<li><a href="ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li>
</ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Accellera" title="Accellera">Accellera</a></li>
<li><a href="Achronix" title="Achronix">Achronix</a></li>
<li><a href="AMD" title="AMD">AMD</a></li>
<li><a href="Aldec" title="Aldec">Aldec</a></li>
<li><a href="Arm_Holdings" title="Arm Holdings">Arm</a></li>
<li><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>
<li><a href="Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>
<li><a href="Intel" title="Intel">Intel</a></li>
<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>
<li><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>
<li><a href="NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li>
<li><a href="Siemens" title="Siemens">Siemens</a></li>
<li><a href="Synopsys" title="Synopsys">Synopsys</a></li>
<li><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li>
<li><a href="Stratix" title="Stratix">Stratix</a></li>
<li><a href="Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Intel Quartus Prime</a></li>
<li><a href="Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>
<li><a href="Vivado" title="Vivado">Vivado</a></li>
<li><a href="ModelSim" title="ModelSim">ModelSim</a></li>
<li><a href="Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li>
<li><a href="List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Intellectual_property" title="Intellectual property">Intellectual<br>property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="ARC_(processor)" title="ARC (processor)">ARC</a></li>
<li><a href="ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>
<li><a href="LEON" title="LEON">LEON</a></li>
<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>
<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>
<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>
<li><a href="Nios_embedded_processor" title="Nios embedded processor">Nios</a></li>
<li><a href="Nios_II" title="Nios II">Nios II</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li>
<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>
<li><a href="OpenCores" title="OpenCores">OpenCores</a></li>
<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a>
<ul><li><a href="OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li>
<li><a href="Power_ISA" title="Power ISA">Power ISA</a>
<ul><li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>
<li><a href="OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li>
<li><a href="RISC-V" title="RISC-V">RISC-V</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div></div><!--htdig_noindex--><div><div class="zim-footer">
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